The information provided below is not admitted to be prior art to the present invention, but is provided solely to assist the understanding of the reader.
Metal-Insulator-Metal Capacitors (MIM Cap) have been integrated in various integrated circuits for applications of analog/logic, analog-to-digital, mixed signal, and radio frequency circuits. The method of fabricating MIM Cap in the current 90 nm technology is described with reference to FIGS. 1A–1G. As shown in FIG. 1A, SiO2 (102) and Si3N4 (103) are deposited in series on a wafer surface with interconnects (101) embedded in an insulator layer 100. In FIG. 1B, the wafer is patterned with an alignment mask to create alignment marks at kerf area 120. In FIGS. 1C and 1D, a first conductive TiN plate (104), a dielectric layer (105), a second conductive TiN plate (106), and a passivation Si3N4 layer (107) are sequentially deposited, and then patterned by masking and etching to obtain a top-electrode (130) of a capacitor. Another Si3N4 layer is then deposited on the wafer, and then patterned by a third masking and etching to obtain a bottom-electrode (150) and insulator (140) of the capacitor as shown in FIGS. 1E and 1F. In FIG. 1G, another insular layer 109 is deposited on the wafer, and then patterned to form electrical contacts 160 and 170.
The above process of record for integrating MIM Cap into back-end-of-line (BEOL) requires three extra masking and etching steps to form the capacitors, which may increase overall fabrication costs. Also, the capacitor-dielectric damage layer, as shown in FIG. 2, resulting from top-electrode over-etch and the poor adhesion between SiN/Cu and SiN/TiN interfaces can cause reliability concerns. Moreover, the capacitor-dielectric thickness is required to be thicker than 500A in order to ensure sufficient process window during top-electrode etch. This requirement limits the extendibility of the process to next technology generations. Furthermore, the high resistivity electrode material, TiN, limits Q factor of the MIM Cap.
A method of manufacturing a capacitor with a compatible copper process is disclosed in U.S. Pat. No. 6,461,914, FIG. 3. However, extra masking and etching steps are required to form the capacitors. Moreover, the capacitor-dielectric layer existing in non-capacitor area will increase the overall structure capacitance, which can increase the interconnect RC delay. Furthermore, the high resistivity electrode material, TaN, limits Q factor of the MIM Cap.
Consequently, products containing MIM capacitors formed by conventional methods are economically uncompetitive in view of their high costs and poor performance. Therefore, a need exists for lower-cost MIM capacitors, formed by methods that result in less damage.
Other objects and advantages will become apparent from the following disclosure.